Optoelectronic device and the manufacturing method thereof

ABSTRACT

An optoelectronic device comprises a semiconductor stack having a first surface, a contact layer having a first pattern on the first surface for ohmically contacting the semiconductor stack, a void in the semiconductor stack and surrounding the contact layer, and a mirror structure on the first surface and covering the contact layer, wherein the first surface has a first portion which is not covered by the contact layer and a second portion covered by the contact layer, and the first portion is rougher than the second portion.

RELATED APPLICATION DATA

This application is a Continuation-in-Part of co-pending U.S. patent application Ser. No. 13/932,661, filed on Jul. 1, 2013, which is a Continuation-in-Part of U.S. patent application Ser. No. 13/528,059, filed on Jun. 20, 2012, now U.S. Pat. No. 8,474,233, which is a Division of Ser. No. 13/021,307, filed on Feb. 4, 2011, now U.S. Pat. No. 8,207,550, which claims priority to U.S. Provisional Patent Application No. 61/302,662, filed on Feb. 9, 2010 under 35 U.S.C. §119(e), the entire contents of all of which are hereby incorporated by reference.

BACKGROUND Technical Field

The application relates to an optoelectronic device and the manufacturing method thereof.

Recently, efforts have been put to promote the luminous efficiency of the light-emitting diode (LED) in order to implement the device in the lighting field, and further conserve the energy and reduce carbon emission. The LED luminous efficiency can be increased through several aspects. One is to increase the internal quantum efficiency (IQE) by improving the epitaxy quality to enhance the combination efficiency of electrons and holes. Another is to increase the light extraction efficiency (LEE) that emphasizes on the increase of light which is emitted by the light-emitting layer capable of escaping outside the device, and therefore reducing the light absorbed by the LED structure.

SUMMARY

The present disclosure provides a novel structure and the manufacturing method thereof for increasing the light extraction efficiency.

One aspect of the present disclosure provides an optoelectronic device comprising a substrate; a first window layer on the substrate having a first sheet resistance, a first thickness, and a first impurity concentration; a second window layer having a second sheet resistance, a second thickness, and a second impurity concentration; and a semiconductor system between the first window layer and the second window layer; wherein the second window layer comprises a semiconductor material different from the semiconductor system, and the second sheet resistance is greater than the first sheet resistance.

One aspect of the present disclosure provides an optoelectronic device comprising a substrate; a metal layer comprising a metal element on the substrate; a first window layer comprising the metal element; and a transparent conductive layer between the metal layer and the first window layer; wherein an atomic concentration of the metal element in the first window layer is less than 1*10¹⁹ cm⁻³.

One aspect of the present disclosure provides an optoelectronic device comprising a substrate; an n-type window layer on the substrate; a semiconductor system on the n-type window layer; a p-type window layer on the semiconductor system; wherein the optoelectronic device emits amber or red light with an optical efficiency at least 70 lumen/watt at a driving current density ranging from 0.1˜0.32 mA/mil².

One aspect of the present disclosure provides a method for manufacturing an optoelectronic device in accordance with the present disclosure. The method comprises the steps of providing a substrate; forming a semiconductor system on the substrate; forming a window layer on the semiconductor system, wherein the window layer comprises a semiconductor material different from the semiconductor system; selectively removing the window layer thereby forming a width difference between the window layer and the semiconductor system, and the width difference is greater than 1 micron.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1H illustrate the corresponding structures fabricated by the manufacturing method step-by-step in accordance with the first embodiment of the present disclosure.

FIG. 2 illustrates an optoelectronic device in accordance with the first embodiment of the present disclosure.

FIG. 3 illustrates an SEM photograph of the optoelectronic device in FIG. 2 in accordance with the present disclosure.

FIG. 4 illustrates a top view of the first ohmic contact layer and the second ohmic contact layer 140 in FIG. 2.

FIGS. 5A to 5E show the corresponding structures fabricated by the manufacturing method step-by-step in accordance with the second embodiment of the present disclosure.

FIG. 6 shows a top-view of the optoelectronic device in FIG. 5E.

FIGS. 7A to 7E show the corresponding structures fabricated by the manufacturing method step-by-step in accordance with the third embodiment of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIGS. 1A to 1H show the corresponding structures fabricated by the manufacturing method step-by-step according to one embodiment of the present disclosure. With reference to FIG. 1A, the method for manufacturing an optoelectronic device in accordance with the present disclosure comprises a step of providing a substrate 101, such as a growth substrate for growing or carrying an optoelectronic system 120, and the material for the substrate 101 includes but is not limited to germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), sapphire, silicon carbide (SiC), silicon (Si), lithium aluminum oxide (LiAlO₂), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (MN), glass, composite, diamond, CVD diamond, diamond-like carbon (DLC), and so on.

A first window layer 111 is formed on the substrate 101 made of a material containing at least one element selected from the group consisting of Al, Ga, In, As, P, and N, such as GaN, AlGaInP or any other suitable materials. The first window layer 111 is a layer with a conductivity-type, such as n-type or p-type (Al_(x)Ga_((1-x)))_(0.5)In_(0.5)P where 0.5≦x≦0.8. The first window layer 111 has two opposite surface wherein the first surface of the first window layer 111 is closer to the substrate 101.

A transition layer could be optionally formed between the substrate 101 and the first window layer 111. The transition layer between two material systems can be used as a buffer system. For the structure of the light-emitting diode, the transition layer is used to reduce the lattice mismatch between two material systems. On the other hand, the transition layer could also be a single layer, multiple layers, or a structure to combine two materials or two separated structures where the material of the transition layer can be organic, inorganic, metal, semiconductor, and so on, and the structure can be a reflection layer, a heat conduction layer, an electrical conduction layer, an ohmic contact layer, an anti-deformation layer, a stress release layer, a stress adjustment layer, a bonding layer, a wavelength converting layer, a mechanical fixing structure, and so on.

Next, the optoelectronic system 120 is formed on the second surface of the first window layer 111 including at least a first layer 121 having a first conductivity-type, a conversion unit 122, and a second layer 123 having a second conductivity-type in sequence. The first layer 121 and the second layer 123 are two single-layer structures or two multiple layers structure (“multiple layers” means two or more than two layers) having different conductivities, electrical properties, polarities, and/or dopants for providing electrons or holes respectively. If the first layer 121 and the second layer 123 are composed of semiconductor materials, such as (Al_(x)Ga_((1-x)))_(0.5)In_(0.5)P where 0.5≦x≦0.8, the first or second conductivity-type can be p-type or n-type. The first window layer 111 has the same conductivity-type as the first layer 121, such as n-type. Besides, the first window layer 111 has greater impurity concentration than the first layer 121 to have a better conductivity. The conversion unit 122 disposed between the first layer 121 and the second layer 123 is a region where the light energy and the electrical energy could transfer or could be induced to transfer. The optoelectronic system 120, such as applied to a semiconductor device, equipment, product, circuit, can proceed or induce the light energy and electrical energy transfer. Specifically speaking, the optoelectronic system includes at least one of a light-emitting diode (LED), a laser diode (LD), a solar cell, a liquid crystal display, or an organic light-emitting diode. The optoelectronic system having the conversion unit 122 transferring the electrical energy to the light energy is a light-emitting diode, a liquid crystal display, or an organic light-emitting diode. The optoelectronic system having the conversion unit 122 transferring the light energy to the electrical energy is a solar cell or an optoelectronic diode. The phrase “optoelectronic system” in the specification does not require that all the sub-systems or units in the system manufactured by semiconductor materials. Other non-semiconductor materials such as metal, oxide, insulator, and so on could also be selectively integrated in this optoelectronic system 120.

Taking the light-emitting diode as an example, the emission spectrum of the transferred light could be adjusted by changing the physical or chemical arrangement of one layer or more layers in the optoelectronic system 120. The commonly used materials are the series of aluminum gallium indium phosphide (AlGaInP), the series of aluminum gallium indium nitride (AlGaInN), the series of zinc oxide (ZnO), and so on. The conversion unit 122 can be a single heterostructure (SH) structure, a double heterostructure (DH) structure, a double-side double heterostructure (DDH) structure, or a multi-quantum well (MWQ) structure. Specifically, the conversion unit 122 comprises a MQW structure comprising a plurality of barrier layers and well layers alternately stacked, each of the barrier layers comprises (Al_(y)Ga_((1-y)))_(0.5)In_(0.5)P where 0.5≦y≦0.8; and each of the well layers comprises In_(0.5)Ga_(0.5)P. Besides, the wavelength of the emitted light could also be adjusted by changing the number of the pairs of the quantum well or the composition of the barrier layer, e.g. the emitted light is red light with dominant wavelength between 600 and 630 nm by having y around 0.7 or amber light with dominant wavelength between 580 and 600 nm by having y around 0.55.

Forming a second window layer 112 on a first surface of the optoelectronic system 120 whose material contains at least one element selected from the group consisting of Al, Ga, In, As, P, and N, such as GaN, AlGaInP or any other suitable materials, and the second window layer 112 comprises at least one material different from the optoelectronic semiconductor system or the second layer 123. The second window layer 112 is preferred a layer with a conductivity-type the same as the second layer 123, such as a p-type GaP layer. In another embodiment, the sidewall of the second window layer 112 and/or the semiconductor system 120 need not be orthogonal to the substrate, but rather may be oblique thereto as indicated in FIG. 3.

Then, forming a first ohmic contact layer 130 formed by conductive material such as BeAu or GeAu alloy on the second window layer 112, and therefore forming a first stack 10 structure as shown in FIG.1A, wherein the first ohmic contact layer 130 comprises a plurality of fingers 132 extending toward borders of the first stack 10 structure as shown in FIG. 4. A first alloying process is then performed at an alloying temperature of around 300˜500° C. or more for forming an ohmic contact between the first ohmic contact layer 130 and the second window layer 112. The detail of the alloying process is well-known for those skilled in this field, and not necessarily disclosed herein.

Next, bonding a temporary substrate 102 formed by supportive material such as glass to the first ohmic contact layer 130 and the second window layer 112 of the first stack structure 10 as shown in FIG. 1B, and removing the substrate 101, and therefore exposing the first surface of the first window layer 111 as shown in FIG. 1C.

Next, forming a second ohmic contact layer 140 formed by conductive material like GeAu or BeAu alloy on the first surface of the first window layer 111, and therefore forming a second stack structure as shown in FIG. 1D, wherein the second ohmic contact layer 140 comprises a plurality of dots that are arranged in a two-dimensional array and is preferred substantially do not overlap with the first ohmic contact layer 130 in vertical direction as shown in FIGS. 1D and for better current spreading effect. A second alloying process is then performed at an alloying temperature of around 300˜500° C. or more for forming an ohmic contact between the second ohmic contact layer 140 and the first window layer 111. The detail of the alloying process is well-known for those skilled in this field, and not necessarily disclosed herein.

Next, a transparent conductive layer 141 is sequentially formed by e-beam or sputtering to cover the second ohmic contact layer 140, wherein the material of the transparent conductive layer 141 comprises metal oxide, such as at least one material selected from the group consisting of indium tin oxide (ITO), cadmium tin oxide (CTO), antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide; and the thickness is about 0.005 μm˜0.6 μm, 0.005 μm˜0.5 μm, 0.005 μm˜0.4 μm, 0.005 μm˜0.3 μm, 0.005 μm˜0.2 μm, 0.2 μm˜0.5 μm, 0.3 μm˜0.5 μm, 0.4 μm˜0.5 μm, 0.2 μm˜0.4 μm, or 0.2 μm˜0.3 μm.

Next, a reflecting layer 150 is formed with a conductive material comprising metal, such as Ag, on the transparent conductive layer 141 as shown in FIG. 1E, and then the reflecting layer 150 is bonded to a supporting substrate 103 by a metal layer 160 as shown in FIG. 1F. In this embodiment, the supporting substrate 103 comprises Si, and the metal layer 160 served as a bonding layer comprises at least one material selected from the group consisting of In, Au, Sn, Pb, InAu, SnAu, and the alloy thereof.

Next, the temporary substrate 102 is removed to expose the first ohmic contact layer 130 and the second window layer 112, and therefore forming a third stack structure. Then the third stack structure is patterned by the lithographic-etching process to form a plurality of chip areas (not shown) on the supporting substrate 103, wherein the etchants of the etching process, e.g. dry-etching chemicals comprising fluoride or chloride etch the second window layer 112 relatively faster than the optoelectronic system 120 such that a first mesa region S1 is formed on the surface of the optoelectronic system 120 or the second layer 123, and the width of the optoelectronic system 120 or the second layer 123 is larger than the width of the second window layer 112 at the interface of the optoelectronic system 120 or the second layer 123 and the second window layer 112 as indicated in FIG. 1G. It can also be noted that a second mesa region S2 is formed on the surface of the first window layer 111, and the bottom width of the first window layer 111 is larger than the optoelectronic system 120 or the first layer 121.

Next, at least the exposed top and sidewall surfaces of the second window layer 112 is wet etched such that the exposed top and sidewall surfaces of the second window layer 112 are roughened, wherein the etching solution, such as a mixture of hydrofluoric acid (HF), nitric acid (HNO₃), and acetic acid (CH₃COOH), etches the second window layer 112 relatively faster than the optoelectronic system 120 such that the width difference L1 is further expanded and become larger, and the second window layer 112 has an enhanced surface roughness higher than that of the optoelectronic system 120, and wherein the width difference L1 is greater than 1 micron and/or less than 10 microns as indicated in FIG. 1H or FIG. 3.

Finally, a first pad 171 is formed on the first ohmic contact layer 130, a second pad 172 is formed on the supporting substrate 103, and a passivation layer 180 covers the second window layer 112 and the first ohmic contact layer 130 to form the optoelectronic device la in accordance with the present disclosure as shown in FIG. 2. The passivation layer 180 serves as a protection layer to protect the optoelectronic device from environment damage, such as moisture, or mechanical damage. The SEM photograph of the optoelectronic device according to one embodiment of the present disclosure is demonstrated as in FIG. 3.

According to one embodiment of the present disclosure, the first window layer 111 comprises semiconductor material, such as (Al_(x)Ga_((1-x)))_(0.5)In_(0.5)P where 0.5≦x≦0.8, and the reflecting layer 150 comprising a metal element, e.g. Ag, is formed after the first and second alloying process such that the metal element in the reflecting layer is less diffused into the first window layer 111, where the first window layer 111 comprises a semiconductor material, preferred a material with substantially the same composition as the first layer 121. According to another embodiment of the present disclosure, the atomic concentration of the metal element in the first window layer is less than 1*10¹⁷ cm⁻³ and the atomic concentration of the metal element is greater than 1*10¹⁶ cm⁻³, therefore causing less degradation to the reflecting layer. The reflecting layer has a reflectivity greater than 90%.

Table 1 shows the optical efficiencies tested under given conditions by the optoelectronic device of the present disclosure. For an optoelectronic device with a small chip size, such as 10 mil², the optical efficiency is as high as about 70 lumen/watt under 20 mA or 0.2 mA/mil² of driving current. For an optoelectronic device with a relative smaller chip size, such as 14 mil², the optical efficiency is as high as about 100 lumen/watt under 20 mA or 0.1 mA/mil² of driving current. For an optoelectronic device with a relative larger chip size, such as 28 mil², the optical efficiency is as high as about 106 lumen/watt under 250 mA or 0.32 mA/mil² of driving current. For an optoelectronic device with a large chip size, such as 42 mil², the optical efficiency is as high as about 121 lumen/watt under 350 mA or 0.2 mA/mil² of driving current. It can be observed from table 1 that the optoelectronic device according to the embodiment of the present disclosure achieves an optical efficiency at least 70 lumen/watt, or preferred at least 100 lumen/watt at a driving current density ranging from 0.1˜0.32 mA/mil².

TABLE 1 the optical efficiencies tested under given conditions according to the optoelectronic device of the present disclosure. Current Optical Dominant Chip Operating density efficiency wavelength size[mil²] current[mA] [mA/mil²] [lumen/watt] [nm] 10 20 0.2 ~70 ~620 14 20 ~0.1 ~90 ~620 28 250 ~0.32 ~106 ~613 42 350 ~0.2 ~121 ~613

According to the present disclosure, the sheet resistance of the first window layer 111 is higher than that of the second window layer 112. Also, the second ohmic contact layer 140 substantially does not overlap with the first ohmic contact layer 130 in vertical direction. Therefore, the driving current is crowding nearby the second ohmic contact layer 140. The light emitted by the optoelectronic device is corresponding to the region of the second ohmic contact layer 140 and is not blocked by the first ohmic contact layer 130, and therefore having the effect of current blocking and benefit to lateral current spreading.

According to another embodiment of the present disclosure, the first window layer 111 comprises a lower impurity concentration than that of the second window layer 112 to have a lower sheet resistance than that of the second window layer 112. According to another embodiment of the present disclosure, the first window layer 111 comprises an n-type impurity with an impurity concentration of around 1×10¹⁷˜5×10¹⁷ cm⁻³, and the second window layer 112 comprises a p-type impurity with an impurity concentration of 1×10¹⁸˜5×10¹⁸ cm⁻³ higher than that of the first window layer 111. According to another embodiment of the present disclosure, the thickness of the first window layer between 1-5 microns is smaller than the thickness of the second window layer 112 between 5-20 microns.

According to one embodiment of the present disclosure, because the sidewall surfaces of the second window layer 112 are roughened, the light can be laterally extracted easily. The chip areas can be rectangle in shape for better luminous efficiency. The ratio of the length to the width of the rectangle is preferred from 1.5:1 to 10:1.

As shown in FIGS. 5A to 5E, a method of manufacturing an optoelectronic device with different structure is disclosed in accordance with one embodiment. The method incorporates the steps as disclosed in FIGS. 1A˜1C and the descriptions thereof. The difference between the optoelectronic devices disclosed in FIG. 5E and in FIG. 2 is the structure between the first window layer 111 and metal layer 160.

Subsequent to the step of removing the substrate 101 and therefore exposing the first surface of the first window layer 111 as shown in FIG. 1C, a second ohmic contact layer 140 formed of conductive material like GeAu or BeAu alloy is formed on the first surface of the first window layer 111, as shown in FIG. 5A, wherein the second ohmic contact layer 140 comprises a plurality of dots that are arranged between any two fingers 132 which are parallel to each other and is preferred not substantially overlapped with the first ohmic contact layer 130 in vertical direction as shown in FIG. 6 so the current spreading is enhanced. As FIG. 6 shows, the pattern of the second ohmic contact layer 140 is aligned with the pattern of the first ohmic contact layer 130. Each of the plurality of dots has at least one bevel. The thickness of each of the dots is about 1000 Å˜10000 Å, and preferably is about 2000 Å˜6000 Å. A second alloying process is then performed at an alloying temperature of around 300˜500° C. or more for forming an ohmic contact between the second ohmic contact layer 140 and the first window layer 111. The detail of the alloying process is well-known to those skilled in this field, and not necessarily disclosed herein.

As shown in FIG. 5B, an insulating layer 142 is formed by e-gun or PECVD to conformably cover the second ohmic contact layer 140 and the first surface of the first window layer 111, wherein the insulating layer 142 is formed of insulating material with refractive index about 1.3˜1.6, such as SiO_(x) or MgF₂. The refractive index of the insulating layer 142 is at least 1.5 lower than that of the first window layer 111. The thickness of the insulating layer 142 is about 500 Å˜5000 Å, and preferably is about 500 Å˜1000 Å. The thickness of the insulating layer 142 is smaller than that of the second ohmic contact layer 140.

Next, as shown in FIG. 5C, the insulating layer 142 is regionally etched by dry etching, such as RIE, or wet etching, such as BOE (buffer oxide etch), to expose the second ohmic contact layer 140. After the etching, a portion of the first surface of the first window layer 111 can be exposed, too. The pattern of the contact layer is complementary to the pattern of the insulating layer.

Next, as shown in FIG. 5D, an transparent conductive layer 141 is formed to cover the insulating layer 142 and the second ohmic contact layer 140, wherein the material of the transparent conductive layer 141 comprises metal oxide, such as at least one material selected from the group consisting of indium tin oxide (ITO), cadmium tin oxide (CTO), antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide; and the thickness is about 50 Å˜150 Å. Then, a reflecting layer 150 is formed on the transparent conductive layer 141, wherein the material of the reflecting layer 150 comprises metal, such as Ag and the thickness is about 2500 Å˜7500 Å. The reflective layer 150 dose not reach the border of the transparent conductive layer 141 and reveals the border region 1431 of the transparent conductive layer 141. In the embodiment, the transparent conductive layer 141 is served as an adhesion layer for improving the adhesion between the reflecting layer 150 and the insulating layer 142.

Then, the reflecting layer 150 is bonded to a supporting substrate 103 by a metal layer 160 and the following process is the same as aforementioned embodiment. The final structure of the optoelectronic device lb is shown in FIG. 5E. The reflecting layer 150 reveals the border region 1431, so a portion of the transparent conductive layer 141 is able to connect to the metal layer 160. In this embodiment, the supporting substrate 103 comprises Si, and the metal layer 160 served as a bonding layer comprises one material selected from the group consisting of In, Au, Sn, Pb, InAu, SnAu, and the alloy thereof. In the embodiment, the insulating layer 142 is capable of preventing the reflecting layer 150 from migrating to the first window layer 111 or the optoelectronic system 120 when an electrical current flows through the reflecting layer 150. The insulating layer 142 is also served as a current blocking. When the electrical current flows through the surface 1111, the electrical current can be blocked by the insulating layer 142 and passes through mainly the second ohmic contact layer 140. In the embodiment, the insulating layer 142 is disposed between the first window layer 111 and the reflecting layer 150, and since the difference of the refractive index between the first window layer 111 and the insulating layer 142 is larger than 1.5, the first window layer 111, the insulating layer 142 and the reflecting layer 150 are able to form an omnidirectional reflector (ODR) for reflecting the light emitted from the conversion unit 122. The reflectivity of the omnidirectional reflector (ODR) is larger than 95%, and preferably is larger than 97%.

FIGS. 7A to 7D show a method of manufacturing an optoelectronic device in accordance with third embodiment of the present disclosure.

The method incorporates the steps as disclosed in FIG. 1A-1C and the descriptions thereof. Subsequent to the step of removing the substrate 101 and therefore exposing the first surface of the first window layer 111 as shown in FIG. 1C, a second ohmic contact region 140 a is formed on the first surface 110 of the first window layer 111 as shown in FIG. 7A. The second ohmic contact region 140 a comprises a plurality of dots formed of electrically conductive material like GeAu alloy or BeAu alloy and arranged between two of fingers 132 parallel to each other as shown in FIG. 6. The second ohmic contact region 140 a is not overlapped with the first ohmic contact layer 130 in vertical direction for enhancing the current spreading performance. Each of the plurality of dots has one bevel. The thickness of each of the dots is about 10 Å˜10000 Å, and preferably is about 50 Å˜6000 Å. Then, a second alloying process is performed at an alloying temperature of around 300˜500° C. or more for forming an ohmic contact between the second ohmic contact region 140 a and the first window layer 111. The detail of the alloying process is well-known to those skilled in this field, and not necessarily disclosed herein.

The first surface 110 of the first window layer 111 has a first portion 111 a exposed by the second ohmic contact region 140 a and a second portion 111 b contacting the second ohmic contact region 140 a. Then, the first portion 111 a of the first surface 110 is roughened by wet etching process using the second ohmic contact region 140 a as a mask such that the first portion 111 a has a first roughness (Ra) during 0.1 μm and 0.5 μm for scattering the light emitted from the conversion unit 122. The wet etching solution used for the wet etching process comprises an acid solution, such as HCl, H₃PO₄ or the combination thereof. In another embodiment, as shown in FIG. 7B, after roughening the first portion 111 a of the first surface 110, a platform 111 d is formed directly under each of the plurality of dots of the second ohmic contact region 140 a, and the area of the dot is smaller than that of the platform 111 d. The platform 111 d has substantially the same shape as the dot 111 d. The platform and the dot thereon are concentric. The platform 111 d comprises a peripheral region not covered by the dot wherein the peripheral region has a smaller roughness (Ra) than that of the first portion 111 a as shown in FIG. 7E, which is an SEM top-view image showing the topography of the roughened first portion 111 a, the platforms 111 d and the plurality of the dots of the second ohmic contact region 140 a. During the wet etching process, the etching solution penetrates into the first window layer 111 approximately at the border 140 a of the second ohmic contact region 140 a to thereby form a void 111 c in the first window layer 111 and surrounds the second ohmic contact region 140 a as shown in FIG. 7C. The void 111 c has a shrinking opening connecting to the border of the second ohmic contact region 140 a. The cross-section of the void 111 c is substantially a triangle or a triangle-like shape and one vertex of the triangle connects to the border of the second ohmic contact region 140 a. Each of the edges of the triangle is smaller than 2 μm and two angles θ₁ and θ₂ between the two edges and the first surface 110 respectively are different. The void 111 c contains air therein. In another embodiment, the cross-sectional shape of the void 111 c comprises an oval.

As shown in FIG. 7C, the method further comprises forming a transparent layer 145 on the first portion 111 a and not covering the second ohmic contact region 140 a. During forming the transparent layer 145, the material of the transparent layer 145 may partially deposit into the void 111 c through the shrinking opening of the void 111 c. The pattern of the transparent layer 145 is complementary to the pattern of the second ohmic contact region 140 a from the top view of the optoelectronic device 1 c as shown in FIG. 7D. The thickness of the transparent layer 145 is between 0.05 μm and 2.5 μm, and preferably has the same thickness as the second ohmic contact region 140 a. The difference between a thickness of the transparent layer 145 and that of the second ohmic contact region 140 a is preferably smaller than 1 μm for reducing the height between the surface of the transparent layer 145 and the second ohmic contact region 140 a. The transparent layer 145 comprises insulating transparent material with a refractive index small than 2, such as SiN_(x), AlO_(x), SiO_(x) or MgF_(x), or conductive transparent oxide material with a refractive index small than 2.2, such as indium tin oxide (ITO), cadmium tin oxide (CTO), antimony tin oxide, indium zinc oxide (IZO), zinc aluminum oxide (AZO), and zinc tin oxide. The refractive index of the transparent layer 145 is different from that of the void 111 c, and the refractive indices of the void 111 c and the transparent layer 145 are both at least 1.0 lower than that of the first window layer 111 for improving the light-extraction efficiency of the conversion unit 122.

As shown in FIG. 7D, the method further comprises forming a reflecting layer 150 conformably covering the second ohmic contact region 140 a and the transparent layer 145 for forming an omnidirectional reflecting structure 144. Since the void 111 c embeds air having a refractive index about 1 and the refractive index difference between the void 111 c and the first window layer 111 is larger than 2, the omnidirectional reflecting structure 144 provides a reflectivity larger than 90% for the light emitted from the conversion unit 122, and preferably larger than 95%. Before forming the reflecting layer 150, the method optionally comprises flattening the transparent layer 145 for further enhancing the reflectivity of the omnidirectional reflecting structure 144. The thickness of the reflecting layer 150 is between 0.1 μm and 1 μm, and preferably is between 0.3 μm and 0.5 μm. The material of the reflecting layer 150 comprises Ag, Au or Al. Then, a barrier layer 151 is formed to conformably cover the reflecting layer 150 for preventing the material of the reflecting layer 150 from migrating when an operating current flows through the reflecting layer 150 and therefore deteriorate the reflectivity of the reflecting layer 150 and the reliability of the optoelectronic device. The thickness of the barrier 151 is between 0.5 μm and 5 μm, and preferably is between 0.5 μm and 1.5 μm. The material of the barrier layer 151 comprises Ni, Ti, Pt, Au or the combination thereof.

Then the barrier 151 is bonded to a supporting substrate 103 by a metal layer 160. In one embodiment, the supporting substrate 103 comprises Si, and the metal layer 160 served as a bonding layer comprises at least one material selected from the group consisting of In, Au, Sn, Pb, InAu, SnAu, and the alloy thereof. The subsequent steps of the method are very similar to or the same as the steps as described in FIGS. 1F˜1H the descriptions thereof, the entirety of which are incorporated into the present embodiment. For example, the temporary substrate 102 is removed to expose the first ohmic contact layer 130 and the second window layer 112, and therefore forming a stack structure. Then the stack structure is patterned by the lithographic-etching process to form a plurality of chip areas (not shown) on the supporting substrate 103, wherein the etchants of the etching process, e.g. dry-etching chemicals comprising fluoride or chloride etch the second window layer 112 relatively faster than the optoelectronic system 120 such that a first mesa region S1 is formed on the surface of the optoelectronic system 120 or the second layer 123, and the width of the optoelectronic system 120 or the second layer 123 is larger than the width of the second window layer 112 at the interface of the optoelectronic system 120 or the second layer 123 and the second window layer 112. It can also be noted that a second mesa region S2 is formed on the surface of the first window layer 111, and the bottom width of the first window layer 111 is larger than the optoelectronic system 120 or the first layer 121. Next, at least the exposed top and sidewall surfaces of the second window layer 112 is wet etched such that the exposed top and sidewall surfaces of the second window layer 112 are roughened, wherein the etching solution, such as a mixture of hydrofluoric acid (HF), nitric acid (HNO₃), and acetic acid (CH₃COOH), etches the second window layer 112 relatively faster than the optoelectronic system 120 such that the width difference L1 is further expanded and become larger, and the second window layer 112 has an enhanced surface roughness higher than that of the optoelectronic system 120, and wherein the width difference L1 is greater than 1 micron and/or less than 10 microns as indicated in FIG. 7D or FIG. 3. Finally, a first pad 171 is formed on the first ohmic contact layer 130, a second pad 172 is formed on the supporting substrate 103, and a passivation layer 180 covers the second window layer 112 and the first ohmic contact layer 130 to form the optoelectronic device 1 c in accordance with the present disclosure as shown in FIG. 2. The passivation layer 180 serves as a protection layer to protect the optoelectronic device from environment damage, such as moisture, or mechanical damage.

FIG. 7D shows an optoelectronic device 1 c with the omnidirectional reflecting structure 144 in accordance with the present disclosure. The optoelectronic device 1 c comprises the first window layer 111, the optoelectronic system 120 on a second surface of the first window layer 111, the second window layer 112 on a first surface of the optoelectronic system 120, the second ohmic contact region 140 a on the first surface of the first window layer 111, the omnidirectional reflecting structure 144 on the second ohmic contact region 140 a and the first surface of the first window layer 111, the barrier 151 completely covering the omnidirectional reflecting structure 144, the metal layer 160 bonding the supporting substrate 103 and the barrier 151, the first ohmic contact layer 130 on the second window layer 112, the first pad 171 on the first ohmic contact layer 130, the second pad 172 on the supporting substrate 103, and the passivation layer 180 covering the second window layer 112 and the first ohmic contact layer 130. The optoelectronic system 120 includes at least the first layer 121 having a first conductivity-type, the conversion unit 122, and the second layer 123 having a second conductivity-type. the omnidirectional reflecting structure 144 includes the void 111 c in the first window layer 111 and surrounding the second ohmic contact region 140 a, the transparent layer 145 on the first surface of the first window layer 112 not covered by the second ohmic contact region 140 a, the reflecting layer 150 conformably covering the second ohmic contact region 140 a and the transparent layer 145. The first ohmic contact layer 130 includes comprises a plurality of fingers 132 and a bonding region 131, wherein the plurality of fingers 132 extends toward the borders of the first stack structure 10 as shown in FIG. 4 and the first pad 171 is formed on the bonding region 131.

The first window layer 111 is made of a material containing at least one element selected from the group consisting of Al, Ga, In, As, P, and N, such as GaN, AlGaInP or any other suitable materials. The second window layer 112 comprises at least one material different from the second layer 123, and is preferred a layer with a conductivity-type the same as the second layer 123, such as a p-type GaP layer. The first mesa region S1 is on the surface of the optoelectronic system 120 or the second layer 123, and the width of the optoelectronic system 120 or the second layer 123 is larger than the width of the second window layer 112 at the interface of the optoelectronic system 120 or the second layer 123 and the second window layer 112. The second mesa region S2 is on the surface of the first window layer 111, and the bottom width of the first window layer 111 is larger than the optoelectronic system 120 or the first layer 121. The top and sidewall surfaces of the second window layer 112 are roughened such that the second window layer 112 has an enhanced surface roughness higher than that of the optoelectronic system 120. The width difference L1 between the optoelectronic system 120 and the first window layer 111 is greater than 1 micron and/or less than 10 microns. The second ohmic contact region 140 a having a plurality of dots ohmically contacts with the first window layer 111 and reveals the first portion 111 a. The first portion 111 a is roughened to have a first roughness (Ra) during 0.1 μ˜0.5 μm for scattering the light emitted from the conversion unit 122. The shrinking opening of the void 111 c connects to the border 140 a of the second ohmic contact region 140 a. The cross-section of the void 111 c is substantially a triangle or a triangle-like shape and one vertex of the triangle connects to the border 140 a. The pattern of the transparent layer 145 on the first portion 111 a is complementary to the pattern of the second ohmic contact region 140 a from the top view of the optoelectronic device 1 c. The refractive index of the transparent layer 145 is different from that of the void 111 c, and the refractive indices of the void 111 c and the transparent layer 145 are both at least 1.0 lower than that of the first window layer 111 for improving the light-extraction efficiency of the conversion unit 122. The reflecting layer 150 conformably covers the second ohmic contact region 140 a and the transparent layer 145 for forming an omnidirectional reflecting structure 144. Since the void 111 c embeds air having a refractive index about 1 and the refractive index difference between the void 111 c and the first window layer 111 is larger than 2, the omnidirectional reflecting structure 144 provides a reflectivity larger than 95% for the light emitted from the conversion unit 122, and preferably larger than 97%. Before forming the reflecting layer 150, the transparent layer 145 is flatted for further enhancing the reflectivity of the omnidirectional reflecting structure 144. The thickness of the reflecting layer 150 is between 0.1 μm˜1 μm, and preferably is between 0.3 μm˜0.5 μm. The thickness of the barrier 151 completely covering the reflecting layer 150 is between 0.5 μm˜5 μm, and preferably is between 0.5 μm˜1.5 μm such that the barrier 151 is able to prevent the reflecting layer 150 from migrating.

It will be apparent to those having ordinary skill in the art that various modifications and variations can be made to the devices in accordance with the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure covers modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.

Although the drawings and the illustrations above are corresponding to the specific embodiments individually, the element, the practicing method, the designing principle, and the technical theory can be referred, exchanged, incorporated, collocated, coordinated except they are conflicted, incompatible, or hard to be put into practice together.

Although the present application has been explained above, it is not the limitation of the range, the sequence in practice, the material in practice, or the method in practice. Any modification or decoration for present application is not detached from the spirit and the range of such. 

1. An optoelectronic device, comprising: a semiconductor stack having a first surface; a contact layer having a first pattern on the first surface for ohmically contacting the semiconductor stack; a void in the semiconductor stack and surrounding the contact layer; and a mirror structure on the first surface and covering the contact layer; wherein the first surface has a first portion which is not covered by the contact layer and a second portion covered by the contact layer, and the first portion is rougher than the second portion.
 2. The optoelectronic device according to claim 1, wherein the contact layer has a border and the void connects to the border.
 3. The optoelectronic device according to claim 2, wherein a cross section of the void is substantially a triangle.
 4. The optoelectronic device according to claim 3, wherein one corner of the triangle connects to the border.
 5. The optoelectronic device according to claim 3, wherein the triangle has two sides connecting to the first surface, and two angles respectively between the two sides and the first surface are different.
 6. The optoelectronic device according to claim 3, wherein a length of one side of the triangle is smaller than 2 μm.
 7. The optoelectronic device according to claim 1, wherein the void contains air.
 8. The optoelectronic device according to claim 1, wherein the first portion of the first surface has a first roughness (Ra) smaller than 0.5 μm.
 9. The optoelectronic device according to claim 1, wherein the mirror structure comprises a transparent layer having a second pattern on the semiconductor stack, a reflecting layer conformably covering the contact layer and the transparent layer.
 10. The optoelectronic device according to claim 9, wherein the second pattern is complementary to the first pattern.
 11. The optoelectronic device according to claim 9, wherein the void has a first reflective index R1, the transparent layer has a second reflective index R2, and R1<R2.
 12. The optoelectronic device according to claim 9, further comprises a barrier layer conformably covering the reflecting layer.
 13. The optoelectronic device according to claim 12, wherein the barrier layer comprises Ti, Pt, Au or the combination thereof
 14. The optoelectronic device according to claim 9, wherein the reflecting layer comprises Ag, Au or Al.
 15. The optoelectronic device according to claim 9, wherein the transparent layer comprises SiN_(x), Al₂O₃, SiO_(x) or MgF₂.
 16. The optoelectronic device according to claim 9, wherein the transparent layer comprises indium tin oxide (ITO), cadmium tin oxide (CTO), antimony tin oxide, indium zinc oxide (IZO), zinc aluminum oxide (AZO), zinc tin oxide.
 17. The optoelectronic device according to claim 9, wherein the transparent layer has a thickness smaller than 2 μm.
 18. The optoelectronic device according to claim 1, wherein the contact layer comprises Ge, Be, Au or the combination thereof
 19. A method of manufacturing an optoelectronic device, comprising the steps of: providing a semiconductor stack having a first surface, wherein the first surface has a first portion and a second portion; forming a contact layer on the second portion of the first surface; roughening the first portion of the first surface; forming a void in the semiconductor stack and surrounding the contact layer; and forming a mirror structure on the first surface to cover the contact layer; wherein the step of forming the void and the step of roughening the second portion are at the same time.
 20. The method of manufacturing an optoelectronic device according to the claim 19, wherein the contact layer has a border and the void connects to the border. 